The present invention relates to a method for the physical placement of an integrated circuit chip that is adaptive to changes made to a netlist.
A highly specialized field, commonly referred to as xe2x80x9celectronic design automationxe2x80x9d (EDA), has evolved to handle the demanding and complicated task of designing semiconductor chips. In EDA, computers are extensively used to automate the design process. Computers are ideally suited to performing tasks associated with the design process because computers can be programmed to reduce or decompose large, complicated circuits into a multitude of much simpler functions. Thereupon, the computers can be programmed to iteratively solve these much simpler functions. Indeed, it has now come to the point where the design process has become so overwhelming that the next generation of integrated circuit (IC) chips cannot be designed without the help of computer-aided design (CAD) systems.
Typically, the design process begins with an engineer conceiving and defining the performance specification of the new IC chip. A high level language is used to translate this specification into functional criteria which are fed into a logic synthesis program. Based thereon, the synthesis program generates a netlist containing a collection of gates in terms of a particular semiconductor technology (e.g., very large scale integrationxe2x80x94VLSI). This netlist can be regarded as a template for the realization of the physical embodiment of the integrated circuit in terms of transistors, routing resources, etc. Next, a physical design tool is used to place and route the IC chip. It determines the physical pinouts, wiring, interconnections and specific layout of the semiconductor chip. Once the physical layout is complete, the IC chip can be fabricated.
In the past, when semiconductor chips were simpler and less complex, the design process was relatively straightforward. However, advances in semiconductor technology have led the way towards more versatile, powerful, and faster integrated circuit (IC) chips. The trend is towards even larger, more complex and sophisticated IC chips in an effort to meet and improve upon the demands imposed by state-of-the-art performance. Today, a single IC chip can contain upwards of millions of transistors. As the complexity, functionalities, speed, and size of these chips increase, it is becoming a much more critical and difficult task to properly design, layout, and test the next generation of chips.
Often, several iterations of the design, layout, and testing process are required in order to optimize the semiconductor chip""s size, cost, heat output, speed, power consumption, and electrical functionalities. However, one problem is attributable to the fact that each of these stages is highly dependent on the results of the other stages. A minor alteration in one stage intended to enhance one characteristic may cause unforeseen problems to occur in other stages. For example, changing a cell in the synthesis stage might drastically alter the current place and route. It is this high degree of interdependence which makes it extremely difficult to predict and account for the consequences associated with any changes. Indeed, the overall design might sometimes be worse in a successive iteration. Furthermore, the iterative process is time-consuming and requires a powerful computer to perform the processing. In addition, the iterative process is labor intensive and requires the dedication of a highly skilled, experienced EDA specialist.
Thus, there is a need for some scheme which cuts the cost and time associated with the semiconductor chip design process, while at the same time, allows a designer to optimize the chip""s performance. The present invention provides one such a solution.
The present invention pertains to a computer controlled method for the rough placement of cells in the design of integrated circuits. Initially, a synthesis tool is used to generate a netlist according to HDL, user constraint, and technology data. Thereupon, a cell separation process assigns (x,y) locations to each of the cells. The cell location information is supplied to the synthesis tool, which can then make changes to the netlist thereto. In the present invention, the size of the placement area is allowed to be scaled according to the new netlist. Next, the cells of the netlist are spaced apart according to a spacing algorithm. A partitioning algorithm is then applied to group the cells into a plurality of partitions. A number of iterations of cell separation, synthesis of new netlist, size adjustment (if necessary), spacing, and partitioning are performed until the cells converge. Thereupon, detailed placement and routing processes are used to complete the layout.